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Dynamic gates use clock for their normal operation as opposed to the static gates, which don’t use clocks. Dynamic gates use NMOS or PMOS logic. It doesn’t use CMOS logic like regular static gates. Because it uses either NMOS or PMOS logic and not CMOS logic, it usually has fewer transistors compared to static gates. Although there are extra transistors given that it uses clocks. The figure shows the pull down NMOS logic for a NOR gate. This pull down structure is used in the dynamic gates. In static gates, inputs switch and after a finite input to output delay, output possibly switches to the expected state. As you can see in the figure above, dynamic gate is made using NMOS pull down logic along with clock transistors on both pull up and pull We know that clock has two phases, the low phase and the high phase. Dynamic gate has two operating phases based on the clock phases. During the low clock phase, because of the pmos gate on the pull up network, the output of dynamic gate is pre-charged to high phase. This When the clock is at high phase, the output of dynamic gate may change based on the inputs, or it may stay pre-charged depending on the input. The phase of the dynamic gates, when the clock is high, is called the evaluate phase. As it is essentially evaluating what the As seen in the waveforms above, as soon as CLK goes low, it pre-charges output node ‘Out’ high. While in the pre-charge state, NOR input ‘A’ goes high. When CLK goes high, and evaluation phase begins, ‘Out’ is discharged to low as input ‘A’ is high. Input ‘B’ is not shown in the waveform as it is not relevant to this case. If both inputs ‘A’ and ‘B’ were to remain low, output node would be held high during the pre-charge. This technique of always priming or pre-charging output to be with, is a way to minimize  switching of the output node, because if with a new set of inputs, output was supposed to be high, it wouldn’t have to switch, as it is already pre-charged. Output  only has to switch