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dexcel is hiring trainee engineers for our validation team. qualification: any graduate in electronics or diploma in electronics location: ba*galore write to [email protected]. company : dexceldesigns location : ba*galore share your resume : [email protected]. skandysys is hiring for physical design freshers for ba*galore location , below is the jd 1. basics of cmos circuits 2. digital design concepts 3. an*lytical skills 4. communication interested candidates can share profile to [email protected] company : skandysys location : ba*galore share your resume : [email protected] hiring asic soc sv, uvm verification trained freshers, we are conducting a hiring drive yet again this week. interested, pls share company : frenustech location : ba*galore share your resume : [email protected] description: • professionals are expected to have good hands-on experience in the following areas: • complete understanding of dft simulation, time closure, area, power, performance, synthesis, sta, route, floor plan, tester application time, and test data volume. • application engineer job opening at synopsys, noida experience: 1 year or m.tech with intern experience in timing, synthesis, formality, lec, formal verification can also apply. interested candidates mail your resume to [email protected] company : synopsys location : noida share your resume : [email protected] test and verification solution!!! our company has urgent opening for following requirement design engineer job title : design engineer job and lint issues. • should be able to understand the tcl files and strong debugging skills is desired. qualification : experience: - 1 years to 2years no. of positions: 6 location: hyderabad notice period – less then 15days those who are interested can forward their resumes to [email protected] or call 08033451855. company : test and verification solution location : ba*galore share your resume : [email protected].